This invention relates generally to memory apparatus using gated phase-change memory cells for information storage.
Phase change memory (PCM) is a non-volatile solid-state memory technology that exploits the reversible, thermally-assisted switching of certain chalcogenide compounds, such as GST, between states with different electrical resistance. The fundamental storage unit (the “cell”) can be programmed to any one of s≧2 different states, or levels, which exhibit different resistance characteristics. The s programmable cell-states can be used to represent different data values, whereby data can be recorded in the cells. In single-level PCM devices, the cell can be set to one of s=2 states, a crystalline state and an amorphous “RESET” state. In the RESET state, the electrical resistance of the cell is high. When heated to a temperature above its crystallization point and then cooled, the chalcogenide material is transformed into its low-resistance crystalline state. If the cell is then heated to a high temperature, above the chalcogenide melting point, the chalcogenide material reverts to the amorphous RESET state on rapid cooling. In multilevel PCM devices, the cell can be set to s>2 different states permitting storage of more than one bit per cell. As well as the two states used for SLC operation, multilevel cells exploit partially-crystalline states in which the cell contains different volumes of the amorphous phase within the crystalline PCM material. Varying the size of the amorphous region produces a corresponding variation in cell resistance. The partially-crystalline states thus provide additional programmable states, with intervening resistance values, between the wholly-crystalline low-resistance state and the high-resistance RESET state.
To write data in PCM devices, cells are programmed to different cell-states by the application of current or voltage signals. Joule heating due to the programming signal heats the chalcogenide material to an appropriate temperature to induce the desired cell-state on cooling. Reading of PCM cells is performed using cell resistance as a metric for cell-state. Read measurements are usually performed by biasing the cell with a fixed read voltage and measuring the resulting current flowing through the cell. A sufficiently low read voltage is used for this resistance metric to ensure that application of the read voltage does not disturb the programmed cell-state. Cell-state detection can be performed by comparing the resistance metric for each cell with predetermined reference levels defining the s programmable cell-states. The larger the resistance difference between the lowest and highest resistance states, the more robust the read-detection process. Hence the amorphous RESET state must have a very high resistance while the fully-crystalline state should have a very low resistance. However, programming via Joule heating requires a large current to pass through the cell. In particular, since power dissipation for a given current decreases with cell resistance, a particularly large cell current is needed to reset a cell from a low-resistance crystalline state to the amorphous RESET state.
Conventional PCM cells are two-terminal devices consisting of a layer of chalcogenide material between a pair of electrodes. To form an integrated memory array, cells arranged in rows and columns are connected in parallel between pairs of word- and bit-lines. An access device, typically an FET (field-effect transistor) whose gate is connected to the word-line, is connected in series with the PCM cell which is connected in turn to the cell bit-line. A particular cell is accessed for read/write operations by applying a word-line voltage to the gate of the associated FET. The programming/read signal is then applied via the cell bit-line.
More recently, gated PCM cells have been proposed. These cells have three terminals, a gate, source and drain, with the PCM material forming a channel between the source and drain. The basic structure of a gated PCM cell is illustrated in FIG. 1 of the accompanying drawings. The cell 1 in this example has chromium source and drain electrodes 2, 3 and a silicon gate electrode 4. A layer of phase-change material provides the channel 5 between the source 2 and drain 3. A gate oxide layer 6 of silicon dioxide lies between the gate 4 and PCM channel 5. Various other materials and layers may be employed in the gated cell structure. In any case, by application of suitable programming signals between the source 2 and drain 3, the PCM material of channel 5 can be caused to switch between amorphous and crystalline states as described earlier, permitting storage of information in the cell. Gated PCM cells are discussed, for example, in: “Prototype of Phase-Change Channel Transistor for both Nonvolatile Memory and Current Control”, Hosaka et al., IEEE Transactions on Electron Devices, 2007, 54, 517-523; and “Multi-bit Storage based on Chalcogenide Thin Film Transistor for High Density Nonvolatile Memory Application”, Yanfei Cai et al., Integrated Ferroelectrics, 110: 34-42, 2009.